IBIS Macromodel Task Group Meeting date: 28 September 2021 Members (asterisk for those attending): Achronix Semiconductor: Hansel Dsilva Amazon: John Yan ANSYS: * Curtis Clark * Wei-hsing Huang Cadence Design Systems: Ambrish Varma Ken Willis * Jared James Google: Zhiping Yang Intel: Michael Mirmak Kinger Cai Alaeddin Aydiner Keysight Technologies: Fangyi Rao Radek Biernacki Ming Yan Todd Bermensolo * Rui Yang Luminous Computing David Banas Marvell Steve Parker Mathworks (SiSoft): * Walter Katz Mike LaBonte Micron Technology: * Randy Wolff Justin Butterfield Missouri S&T Chulsoon Hwang Siemens EDA (Mentor): * Arpad Muranyi Teraspeed Labs: * Bob Ross Zuken USA: * Lance Wang The meeting was led by Arpad Muranyi. Curtis Clark took the minutes. -------------------------------------------------------------------------------- Opens: - None. ------------- Review of ARs: - None. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the September 21st meeting. Randy moved to approve the minutes. Bob seconded the motion. There were no objections. ------------- New Discussion: PAMn BIRD213.1 draft 6: Arpad said he had two suggested changes: 1. In the Definition of the Issue section, the enumerated list of values of n should include 4 (i.e., PAM4). Walter agreed and added 4 to the list. 2. In the Solution Requirements section, the last bullet refers to "legacy PAM4 keywords". Arpad said the term "legacy" is nebulous because it is relative to a particular version of IBIS. Walter agreed and removed the word legacy. Walter noted that once Arpad's BIRD214 (bit_time -> symbol_time) is accepted into IBIS 7.1, several sections referring to bit_time will be rewritten to use symbol_time. Walter suggested we table this BIRD until IBIS 7.1 is approved. Walter said he would then update the BIRD's language so that it is relative to IBIS 7.1. Randy asked if we will have to add something to the descriptions of the existing PAM4 keywords to acknowledge the overlap with the new PAMn keywords. Walter said he did not think this would be a significant effort, and he suggested we deal with it when the BIRD is updated relative to IBIS 7.1. GDDR6X update: Walter shared his GDDR6X presentation and said it contained some of his initial thoughts as he considered Arpad and Randy's "GDDR6X IBIS Modeling" presentation from the DesignCon IBIS Summit. slide 2: GDDR6X Supporters - Micron - Nvidia - Mentor Arpad noted that the Verilog-A model he had developed for the multi-level Tx should be recognized by any EDA tool that supports the multi-lingual [External Model] keyword in IBIS. slide 3: What is GDDR6X? - Memory Interface - DQ/DQS Clock forwarded - DQ is single-ended PAM4 - Approx 20 Gbps - Loss at Nyquist ~10 dB - Loss at 1/(Rise Time) ~50 dB Walter said his assumptions about losses were based on some experience with Ethernet backplanes. He said at these data rates it's hard to get a channel that is better than 10 dB, and you can do much worse. He said for this memory interface he's guessing 10 dB at Nyquist and about 60 dB at the edge rate. He said an 8" trace on FR4 would give you this type of loss. Walter asked if anyone had any comments on these rough assumptions, and no one offered any. slide 4: What are the issues? - PAM4 Vertical non-linearities - 4 Levels not uniformly spaced - 12 different transitions have different edge rates and skews - Drive impedance at the 4 levels may differ Walter noted that the level spacing non uniformity could be an issue for differential PAM4 but is likely a bigger issue for single-ended PAM4. slide 5: Rising and Falling Edge Simulation Results - Level 0, 2, 3 are uniformly spaced. - Level 1 is off by about 10 mV slide 6: SPICE vs AMI Comparison (Ideal Tx) The slide shows an eye diagram presented at the summit. Walter noted that with an ideal AMI Tx you're going to get uniform spacing between the levels. However, the level 1 from the SPICE simulation is off by about 10mV. This non- linearity could be caused by many things. The AMI simulation results are going to be optimistic in this case. slide 7: SPICE vs AMI Comparison (Full swing IBIS buffer Tx model) This slide from the summit presentation shows better agreement with SPICE, but there are still issues modeling the non-linearities and transition timing. slide 8: SPICE vs multi-edge AMI Comparison (Full swing IBIS buffer Tx model) This slide from the summit presentation shows better agreement with SPICE in terms of some edge shapes, but there are still issues modeling transition timing. Walter said slides 6 through 8 show that there are issues you can't model with AMI_Init statistical processing. You'd be optimistic because of the non-linearities you can't model, and the only way to deal with it would be margining (for example, reducing the predicted eye opening by 5 or 10 mV of noise). slide 9: Various level transitions This slide from the summit presentation shows IBIS Tx buffer rising and falling transition waveforms extracted from the SPICE model for all 12 possible state transitions. Walter wondered how important the edge rate differences in these transitions would be after you go through a channel that is 60 dB down at the edge rate. He suggested that instead of extracting the transitions when driving a simple resistive load (typical IBIS waveform extraction fixture), the SPICE simulation be redone using 8" of FR4 or some non-low-loss material. He predicted that the edges would all look similar at the Rx end of the channel. Since AMI only cares about the step response at the receiver, he wondered if the multiple transition waveforms would add any value for AMI. slide 10: AMI Statistical Analysis Walter suggested that the different skews and slew rates for the 12 transitions could be modeled with statistical AMI Reserved parameters. In this case, for example, a 5ps jitter. Vertical non-linearity would also have to be handled statistically, in this case a 10mV noise margin. slide 11: AMI Time domain Analysis Walter proposed that Tx AMI_GetWave could modify the input stimulus waveform to account for some of the non-linearities. The ideal input stimulus waveform could be modified so that the transition timing and level for each transition could be modeled. The transitions' edge timings and levels could be stored as tables in the model and utilized for each type of transition. Walter said he would prefer to avoid the additional complications of introducing new [Rising Waveform]s and [Falling Waveform]s for all of the transitions. He said we could leave it to the Tx AMI model maker to model the relevant effects. Randy said he was also resistant to the idea of adding new I-V and V-T tables to the IBIS [Model]. He said doing so might yield a good model for this particular implementation of a driver with two pullup and two pulldown legs, but it may not be what other driver architectures would require. Bob noted that Fangyi, et. al., had submitted a paper on single-ended PAM4 in AMI for the upcoming IBIS Summit in Japan. (November 12th) Arpad asked how the AMI_GetWave approach could capture the interaction between a driver attempting to drive a certain level into the channel with reflections, crosstalk, etc. He said that interaction is lost with an AMI_GetWave approach with a "hardcoded" output voltage level. Walter said we are stuck with that limitation in IBIS today. We know the impedance of a driver in the high state and in the low state, but IBIS provides no information about what the impedance is during a transition between the two. Walter said he thought the device designers would work very hard to make the impedances the same at all 4 output levels. He said this issue isn't a big deal for differential because you care about the differential impedance, but for single-ended you could create a PAM4 driver with a huge vertical non-linearity. He said he expected device makers to work very hard to avoid that. Walter asked about any rough deadlines for us to deliver a solution. When will GDDR6X users need to verify their system designs? Will we need to update IBIS? Walter said he hoped the modeling issues could all be addressed with Model Specific parameters or hard coded in the .dll. He said we could put the onus on the model maker to model these effects, and we should start conversations with EDA vendors, device makers, and end users to find an approach that works for all of them. - Walter: Motion to adjourn. - Randy: Second. - Arpad: Thank you all for joining. AR: Walter to send his GDDR6X presentation to the ATM list. ------------- Next meeting: 05 October 2021 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives